Overcoming the Limitations of Accelerator-Centric Architectures with Memoization-Driven Specialization

Abstract

Modern computer systems are undergoing a paradigm shift towards specialized architectures that improve computation efficiency by orders of magnitude. At the core of specialized architectures are ``accelerator'' chips that are designed to target specific computation domains and achieve better gains under a given hardware budget. Accelerator-centric chip specialization has become one of the leading approaches to mitigate the gap between the growing computation demands and the dwindling improvement in CMOS chips' budget and capabilities imposed by the end of Moore's law and failure of Dennard scaling.

The accelerator approach suffers from several inherent caveats. (i) While domain-specific accelerators improve the gains of a non-improving CMOS budget, they are implemented using CMOS transistors. Therefore, accelerator chips are susceptible to the end of CMOS scaling. Much like general-purpose chips, their gains will be capped following the end of CMOS scaling, and: (ii) the targeting of specific domains requires the sacrificing of programmability, which makes ASIC accelerators limited in their ability to efficiently accommodate new applications and features, due to the long process of ASIC accelerator development.

In this dissertation, we explore the limits of accelerators imposed by the combination of transistor-dependence and diminishing specialization returns. We develop architectures that employ memoization to extend the reach of traditional hardware specialization by alleviating transistor-dependence and loss-of-programmability in accelerator-centric architectures.