Development of Automated Toolchain on Synthesizing Domain-Specific FPGAs

Abstract

Designing custom FPGAs is a complex process. The process often involves immense trade-off on area and power in order to achieve performance increase for specific operations along with huge human effort. This paper explores the possibility of an automated toolchain that allows users to customize FPGAs by integrating accelerators onto the FPGA to maximize the performance increase within the same area and power usage. The toolchain can identify common patterns in application RTLs using frequent subgraph algorithm and then merge found common patterns into a domain-specific accelerator. The accelerator then can be hardened using open-source tools such as PRGA, OpenLANE, and Yosys. Hardened accelerator then can be integrated onto the FPGA and replace some of the lookup tables and their interconnects. Hardened accelerator will allow the user to use less lookup tables to run the same application at an increased performance. With the whole process being automated, the FPGA can be easily specialized while using the same die area and possibly less power by running the combinational logic accelerator rather than running lookup tables.