Compensation for the Error/Non-Ideality in Data Conversion and Transmission Using Statistical Estimation and Coding Techniques

Abstract

Since Moore's law was initially presented in 1965, shrinking transistors have driven advances in integrated circuits (ICs), resulting in tremendous innovations and increased capacity of computing. However, after 50 years of scaling, as technology nodes have progressed into nanometer scale, fundamental limitations (e.g., physical restrictions, increasing leakage, thermal issues, etc.) make further scaling harder, and limit performance improvements. This motivates a rethinking of computation from traditional deterministic approaches to statistical approaches, due to increasing statistical behavior of devices. This thesis investigates two manifestations of statistical errors, the first in data conversion in analog circuits, and the second in data transmission for energy-efficient applications in digital circuits. In the analog domain, device variation results in offset voltage of comparators, giving rise to comparison errors in data conversion. In the digital domain, heterogeneous architectures integrating specialized hardware enable better energy efficiency. The memory accesses and data communication limit energy consumption. To address the energy, low-swing signaling is employed at the cost of bit errors.

In this thesis, rather than overcoming the device-level offset, we exploit the error statistics for data conversion and propose an architecture to build an accurate analog-to-digital converter (ADC) composed of inaccurate comparators, while providing a better trade-off between power/area and accuracy than previous approaches. We present a statistical ADC using approximate maximum-likelihood estimation, achieving higher resolution than any previously reported statistical ADC work, and explore the potential for enhancing both the achievable dynamic range and energy efficiency by employing pipelining and sub-ranging.

To address memory accesses and data communication, we investigate an accelerator-based 3D architecture, which provides each accelerator direct access to its local memory through short-distance vias, as well as access to other long-distance memories through route- and swing-configurable paths. To reduce the energy consumed on transmission paths, we explore low-swing signaling. Although the highly regular and differential structure of SRAM enables aggressive swing reduction, and thus considerable energy saving, the reduction of swing inevitably makes the system error-prone. We employ coding techniques to correct the error due to the reduced swing.