FinFET-based SRAM and Monolithic 3-D Integrated Circuit Design

Abstract

Device miniaturization enabled processors to become faster and more powerful for decades. However, device scaling became more challenging due to increasing leakage power consumption, intolerable short-channel effects (SCEs), and manufacturing costs. This thesis aims to develop newer approaches for low-power and high-performance designs for next generation computing technologies. It focuses on two research directions: FinFET-based static random access memory (SRAM) design and hybrid monolithic 3-D integrated circuit (IC) design.

The first research direction is to design area-efficient, low-power, and high-performance SRAM cells. To this end, we investigate two approaches: multi-parameter asymmetric (MPA) FinFET-based SRAM design and 3-D transistor-level monolithic (TLM) SRAM design. In the first approach, we use FinFETs with up to three asymmetries to address various SRAM challenges such as high leakage power, read-write conflict, and width quantization issue at once. We present five new 6T SRAM cells using MPA FinFETs and provide a comprehensive evaluation of SRAM cells based on asymmetric FinFETs. We show MPA FinFETs can achieve high stability metrics and reduce leakage power significantly at a cost of degraded performance. We investigate TLM technology in the second approach of SRAM design. In 3-D TLM design, n- and p-type transistors are fabricated on different layers. Conventional 6T/8T SRAM cells have an area inefficiency when implemented in 3-D due to the unequal number of n- and p-type transistors in the cell. We present two new 3-D 8T SRAM cells that consist of four n-type and four p-type transistors for better area efficiency. The proposed cells provide superior read performance and lower leakage power consumption when compared to other 2-D/3-D SRAM cells at a cost of degradation in writeability.

The second research direction of this thesis is to explore the benefits of monolithic 3-D design from circuit to multi-core system level. 3-D ICs can address design challenges such as the interconnect bottleneck and memory wall. 3-D ICs reduce power consumption, delay, and interconnect length by utilizing the vertical dimension. Among 3-D IC solutions, monolithic 3-D technology appears to be very promising as it provides the highest connectivity between transistor layers owing to its nanoscale monolithic inter-tier vias (MIVs). Monolithic 3-D integration can be realized at different levels of granularity such as block, gate, and transistor. In this thesis, we focus on hybrid monolithic (HM) designs, which combine modules implemented in different monolithic styles to utilize their advantages. We develop the tools that are needed to explore the HM design space. We develop a 3-D HM floorplanner, gate-level placement methodology, and modeling tools for logic, memory, and NoC modules. We integrate these tools into McPAT-monolithic, an area/timing/power architectural modeling framework we develop for HM multi-core systems.