Challenges and Opportunities in Future Multi-Chiplet Architectures

Abstract

The slowdown of Moore's Law has decreased the rate that transistor density has been increasing in silicon chips. These circumstances increasingly force computer architects to use multi-chiplet designs that divide the logic between multiple dies in a single package. The contemporary designs use the multi-chiplet paradigm to provide a one-time alleviation of the aforementioned problems. Moreover, multi-chiplet architectures introduce new challenges, including increased simulation complexity and higher inter-core latencies. At the same time, this paradigm creates new exciting opportunities, including post-tapeout heterogeneous integration and high bandwidth on-package interconnects. This dissertation aims to investigate the challenges and opportunities of multi-chiplet architectures deeper and provide the means of continuous performance scaling using chiplet design. First, it shows that the future scaling of on-package interconnects is a valuable resource that can increase the performance of multi-chiplet systems. In particular, it demonstrates that the old idea of bandwidth-demanding write-update coherence protocols adapted for modern multi-chiplet systems significantly improves their performance. Moreover, it shows that the performance improvement will continue to grow in the future systems and provide the source of continuous performance scaling. Second, this dissertation discusses the issues involved with modeling multi-chiplet architectures in current software simulators. It introduces SMAPPIC, a novel prototyping platform for large multi-chiplet systems using a cloud multi-FPGA setup that enables fast, scalable, accurate, and economic multi-chiplet modeling. It describes the platform's design and demonstrates many use cases enabled by SMAPPIC. The new tool promises to ease the burden of multi-chiplet modeling and provide a continuous source of optimizations in the future. Third, this dissertation discusses the problem of combining chiplets from different vendors in one heterogeneous System-in-Package. It shows how various competing coherent on-package interconnect standards can become a problem for future multi-chiplet systems and proposes Rosetta: an architecture for coherent inter-chiplet interconnect translation. Rosetta erases the boundaries of coherent on-package interconnect standards and enables future multi-chiplet systems to be more flexible and efficient with each new generation. Finally, this dissertation puts the proposed solutions in the context of previous works and discusses the prospects of multi-chiplet systems.