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Title: Architectural Support for Scalable High-Bandwidth I/O
Authors: Lavrov, Alexey
Advisors: Wentzlaff, David
Contributors: Electrical Engineering Department
Keywords: hardware transport protocol
scalable I/O
Subjects: Computer engineering
Issue Date: 2020
Publisher: Princeton, NJ : Princeton University
Abstract: The number of cores in modern-day processors keeps growing and it has already reached hundreds of cores per socket. This trend, combined with improvements in virtualization technologies, results in many independent tenants sharing a single server. Available local server interconnect and network bandwidth is growing as well, moving to a terabit per second speeds. Efficient link and processor utilization in environments with thousands of tenants sharing an I/O device introduces unique challenges and requires rethinking existing hardware architectures. As the number of tenants increases, contention for shared resources can degrade total performance. In this thesis, compute environments with many independent tenants sharing a single server are referred to as hyper-tenant environments. A high-bandwidth network requires significant CPU involvement to handle transport protocol operations. In cloud datacenters, these CPU resources can also be sold to customers running their applications. Therefore, datacenter providers need to decrease CPU involvement in network transport protocol operations. This can be achieved by performing common protocol operations in hardware. However, there are multiple transport protocols used in datacenters. On top of that, the hardware design should support thousands of connections due to the high workload consolidation ratio. This thesis presents an analysis of current I/O address translation schemes and studies of their scalability in hyper-tenant setups. Based on the conclusion from the analysis, it introduces a new design for hyper-tenant I/O address translation. Furthermore, this thesis describes a new trace-based simulator, which allows us to study various system parameters. This thesis describes the architecture of scalable hardware units used to perform the common operations between multiple network protocols to offload a portion of the networking stack from software on general purpose a processor to hardware. The units are combined into a configurable design, which supports thousands of concurrent flows and can fully utilize a 100Gb/s link. Finally, this thesis covers an I/O interface for communication between a hardware testbench and a host machine. The presented design can execute both assembly tests and an operating system without physical access to hardware across a variety of platforms to enable automated testing.
Alternate format: The Mudd Manuscript Library retains one bound copy of each dissertation. Search for these copies in the library's main catalog:
Type of Material: Academic dissertations (Ph.D.)
Language: en
Appears in Collections:Electrical Engineering

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