Open Source Platforms for Enabling Full-Stack Hardware-Software Research

Abstract

Hardware-software research routinely starts with modelling. High-level models can capture much of the desired system behaviour needed to begin evaluating architectural research ideas. However, when those ideas come closer to realisation in real chips or they focus on cross-layer optimisations, higher-fidelity modelling tools must be brought to bear in evaluating them. This dissertation focuses on the development of two such tools, intended to enable research across the hardware-software stack. The tools described in this dissertation have been open-sourced in both their designs and characterisation in order to enable others to evaluate their research ideas with high fidelity. The first tool is OpenPiton, a full-stack manycore research platform and the world’s first open-source, general-purpose, multithreaded manycore processor. OpenPiton provides a toolbox for researchers to design new manycore processors incorporating their chosen research modifications. This toolbox includes scripts and tools necessary to produce a variety of processor configurations and take those instances all the way to realisation in real silicon chips. By embracing open-source design, the system supports modification at all levels of the stack, from underlying circuits to software running above, and as a result has been adopted in a variety of research areas across computing. The second tool presented in this dissertation is the Bring Your Own Core (BYOC) platform. BYOC is designed to enable heterogeneous-ISA systems research in architecture, systems software, and languages. BYOC brings together cores of multiple ISAs in a single, cache-coherent, manycore system and introduces a new interface for new cores to be rapidly connected to the system. This dissertation describes the integration of several new cores into OpenPiton to build this BYOC platform and the means taken to specifically support these cores existing together in a heterogeneous configuration, such that they can communicate via high-bandwidth and low-latency cache-coherent shared memory. This dissertation also details a characterisation of an FPGA prototype named Dicho, built with a combination of an OpenSPARC T1 SPARC V9 core and an Ariane RISC-V core.