Heterogeneous Architectures for Superconducting Quantum Computing

Abstract

Since their advent more than two decades ago, superconducting quantum devices have been a leading platform for quantum computation. Year by year, coherence times increase, gate errors decrease, and new records are set for the number of qubits in a system. As the challenges of scaling continue to accumulate, there is more room than ever for innovation at all levels of the quantum computing stack. This thesis explores the concept of heterogeneity in superconducting quantum computer design at two different levels. At the level of the two-qubit entangling gate, this thesis investigates two novel tunable coupler architectures for parametric gates. Devices are designed to optimize the trade-off between gate speed and fidelity while providing a platform to study leakage outside the computational subspace. At the quantum computer architecture level, we design and simulate a heterogeneous architecture for lattice surgery of surface codes based on ideas from quantum networking. A co-design approach leads to a hardware-aware error-correcting architecture that aims to improve the efficiency of Pauli-based computation.