Interfacing FPGA with Open Source Processor: OpenLane & Caravel

Abstract

The results of this project culminated from several approaches to learning and using OpenLane/OpenROAD and Caravel. At first I was introduced to the OpenLane/OpenROAD Project, an RTL to GDSII flow created by Efabless. An extension of OpenLane is Caravel, a "template SoC" according to Efabless, which can be used by third-party developers to implement their own designs within a provided project space on the Caravel chip. With Caravel, I endeavored to implement an interface which could serialize large buses of data, and forward them to an FPGA as a bitstream in order to program it. In order to be compatible with Caravel, the specific interface needs to be compliant with the Wishbone Protocol specifications, which will be the Wishbone B4 Spec from OpenCores. The FPGA to be connected through this interface is a Scanchain FPGA designed for submission to Efabless's MPW6 tapeout program, one of several designs in the Princeton Reconfigurable Gate Array (PRGA). With extensive support and knowledge from Graduate Student Ang Li, and his work and experience on PRGA itself, I hoped to create a synthesizable Wishbone interface in Verilog HDL that could program the FPGA externally with Caravel's on-chip RISC-V processor. Ultimately, I managed to create an interface that properly serializes and sends the correct data, but I did not have enough time to program the FPGA with a full configuration. I will discuss the possible the methods by which this could be implemented in the future.