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Authors: Chaudhuri, Sourindra Mohan
Advisors: JHA, NIRAJ K
Contributors: Electrical Engineering Department
Subjects: Electrical engineering
Issue Date: 2015
Publisher: Princeton, NJ : Princeton University
Abstract: Recently, multi-gate transistors have been gaining attention as an alternative to conventional metal oxide semiconductor field-effect transistors (MOSFETs). Superior gate control over the channel, smaller subthreshold leakage, and reduced susceptibility to process variations are some of the key features that give multi-gate structures a competitive edge over planar MOSFETs. Among various multi-gate structures, silicon-on-insulator (SOI) FinFETs are promising owing to their ease of fabrication. However, cost-effective large-scale fabrication, efficient device simulation, accurate device/gate level characterization, smart power optimization, and novel circuit/architectural design are few key areas that need immediate attention in order for FinFETs to gain greater popularity in this decade. This thesis first focuses on developing efficient device simulation techniques to ease characterization of FinFET devices/logic gates under process-voltage-temperature (PVT) variations. Next, it proposes several power optimization techniques enabled by different implementation styles that are unique to FinFETs. Ideally, 3D device simulation should be done for accurate characterization of FinFET devices and logic gates, but this is impractical due to the huge CPU time required for such simulations. In this thesis, we address this issue by proposing a methodology to obtain gate underlap (LUN)-adjusted 2D models for FinFETs that very accurately track 3D device behavior. Thus, we achieve 3D simulation accuracy with 2D simulation efficiency. To the best of our knowledge, this is the first such attempt. We also show that 2D device models remain valid even under PVT variations. Though adjusted 2D models can accurately track 3D FinFET device behavior, obtaining accurate 3D FinFET structures remains a prerequisite. CPU-intensive process simulation is necessary to capture all device-related physical phenomena of a 3D FinFET. Creating a process-simulated device (PSD) structure can be seen as a one-time cost for a given technology node. However, device simulation using these 3D PSD structures is also very time-consuming. Adoption of any new device requires a thorough characterization of the device and complete logic cell library. This involves a large number of simulations under PVT variations. Whereas performing these simulations with 3D PSD structures is impractical, performing a large number of variation simulations with adjusted 2D cross-sections is also time-consuming. For the first time in this thesis, we show that the states obtained from quasi-stationary (QS) simulation of a nominal device can assist in significantly reducing simulation time of similar devices under process-voltage (PV) variations. This adjusted-assisted technique is limited to QS simulations under PV variations. Hence, in order to aid circuit designers, we also present accurate analytical models using central composite rotatable design based on response surface methodology to estimate the leakage current and delay of FinFET standard cells under PVT variations. This thesis also proposes techniques to optimize power consumption of FinFET based circuits. FinFETs can be operated in two different modes: shorted-gate (SG) or independent-gate (IG). SG and IG FinFETs may be symmetric or asymmetric. Conventional SG/IG FinFETs are symmetric. Since asymmetric SG FinFETs have better device characteristics than asymmetric IG FinFETs, we concentrate on the former. Among asymmetric SG FinFETs, asymmetric-workfunction SG (AWSG) FinFETs are notable for their ultra-low-leakage power consumption, two orders of magnitude lower than that of symmetric SG FinFETs, but at the expense of some delay penalty. We present a delay-constrained power optimization methodology in which the negligible amount of leakage power consumed by AWSG cells plays a pivotal role. We use a higher supply voltage to reduce the delay of AWSG logic circuits so that they become delay-competitive with SG FinFET logic circuits. This does increase the dynamic power consumption. However, the reduction in leakage power is so drastic that the total power still goes down significantly. The advantage increases at higher operating temperatures. Previously, researchers have primarily explored FinFETs with asymmetry in just one parameter: AWSG, asymmetric doping SG (ADSG), asymmetric underlap SG (AUSG), and asymmetric gate-oxide IG (AOIG). Although, AWSG FinFETs have been explored in the context of both logic and memory, ADSG and AUSG FinFETs have only been explored in the context of SRAM cell design. In this thesis, for the first time, we analyze multiparameter asymmetric SG FinFETs and illustrate their potential for implementing logic gates and circuits that are both ultra-low-leakage and high-performance simultaneously. We show that logic gates and circuits based on asymmetric workfunction-underlap SG (AWUSG) FinFETs provide higher performance at much less leakage power as well as less area compared to gates/circuits based on traditional SG FinFETs.
Alternate format: The Mudd Manuscript Library retains one bound copy of each dissertation. Search for these copies in the library's main catalog
Type of Material: Academic dissertations (Ph.D.)
Language: en
Appears in Collections:Electrical Engineering

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