Skip navigation
Please use this identifier to cite or link to this item:
Title: Logic Optimization for Binary Decoder Circuits - Simultaneous Area and Timing Optimization
Authors: Tennant, Matthew
Advisors: Malik, Sharad
Department: Electrical Engineering
Class Year: 1998
Extent: 23 Pages
Other Identifiers: 9781
Location : This thesis can be viewed in person at the Mudd Manuscript Library. To order a copy complete the Senior Thesis Request Form. For more information contact
Type of Material: Princeton University Senior Theses
Appears in Collections:Electrical Engineering, 1932-2020

Files in This Item:
There are no files associated with this item.

Items in Dataspace are protected by copyright, with all rights reserved, unless otherwise indicated.