Instruction-Level Abstraction for the NVIDIA Deep Learning Accelerator: Convolution Datapath

Abstract

Accelerators are becoming integral to computing systems because they efficiently handle tasks offloaded from other processors. This has sparked great interest in the design of these hardware units and the interfaces they expose to the computing systems they integrate into. Yet despite the attention given to their design and utility, accelerators still lack formal specifications that define their interactions across the hardware-software interface. The lack of formal specifications creates challenges in developing verification techniques that are scalable and compatible with a wide range of accelerators.

In this work, I apply the semantics of Instruction-Level Abstraction (ILA) to formalize a significant subset of the NVIDIA Deep Learning Accelerator (NVDLA). My model highlights the software-visible characteristics of two arithmetic units within NVDLA's convolution pipeline while providing an interface useful for simulation, formal verification, and compiler optimizations.