Please use this identifier to cite or link to this item: http://arks.princeton.edu/ark:/88435/dsp01q237hr980
 Title: Low-power FiNFET circuit design and synthesis under spatial and temporal variability Authors: Mishra, Prateek Advisors: JHA, NIRAJ K Contributors: Electrical Engineering Department Keywords: CADDESIGNFINFETTRI GATE Subjects: Computer engineeringElectrical engineering Issue Date: 2012 Publisher: Princeton, NJ : Princeton University Abstract: Moore's law has enabled the scaling of CMOS technologies over the past several decades. However, the scaling of conventional transistors beyond 22nm is limited by various factors, such as power consumption and process variation effects. With every successive technology generation, leakage current has been increasing exponentially due to the various short-channel effects, such as thresh- old voltage (Vth) roll off, drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL). Thus, the major challenge in continuing the Moore scaling lies in controlling the short- channel effects. Double-gate field-effect-transistors (DGFETs) have been proposed as a promising alternative to the conventional transistor technology. Due to the superior electrostatic integrity of the channel, provided by the double-gate structure, they can significantly mitigate the effects of short-channel effects. Thus, they have been proposed as an attractive solution for scaling beyond 22nm. Among DGFETs, FinFETs have recently attracted a lot of attention due to their superior fab- ricatability. The fabrication process of FinFETs is quite similar to that of conventional transistors. FinFETs are quasiplanar structures in which the channel is made to stand up on its edge. Fin- FETs consist of a thin silicon fin around which a gate electrode is wrapped. This results in a dual/tri-gate structure, depending upon the thickness of the oxide at the top of the channel. Fin- FETs have also been shown to have a superior ION=IOFF ratio as compared to the conventional transistor at the same technology node. Hence, FinFETs can be used to increase performance and reduce leakage current of a chip simultaneously. The two gates of the FinFET can be made indepen- dent of each other by etching out the top portion of the FinFET. Such FinFETs have been exploited by researchers to develop various innovative standard cell designs. Also, the Vth of the front gate of the FinFET can be controlled by applying a bias to its back gate. Since Vth controls both the subthreshold leakage and the delay of a logic gate, the back-gate bias can be used as an important knob to optimize the delay and power of circuits that employ independent-gate FinFETs. Another important property of FinFETs is that they can be easily fabricated along the < 110 > channel orientation by rotating the fins by 45o from the < 100 > wafer plane. Since the electron mobility is maximum along the < 100 > channel orientation and the hole mobility is maximum along the < 110 > channel orientation, optimized logic gates can be built by fabricating the pull-up network of the logic gates in the < 110 > channel orientation and the pull-down network in the < 100 > channel orientation URI: http://arks.princeton.edu/ark:/88435/dsp01q237hr980 Alternate format: The Mudd Manuscript Library retains one bound copy of each dissertation. Search for these copies in the library's main catalog Type of Material: Academic dissertations (Ph.D.) Language: en Appears in Collections: Electrical Engineering

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