Please use this identifier to cite or link to this item: http://arks.princeton.edu/ark:/88435/dsp01hx11xf359
 Title: Power Modeling of Microprocessors via Emulation on a Field Programmable Gate Array Authors: Batchelder, Rachael Advisors: Wentzlaff, David Department: Electrical Engineering Class Year: 2013 Abstract: The power dissipation of microprocessors has become an increasingly important issue in their design for reasons including energy efficiency and transistor performance. Designers often use modeling software to analyze the power characteristics of a processor before it is built because of the long time and effort required to construct physical hardware. These models can vary in level of detail, speed of computation, and accuracy, but are very reliant on the characteristics of ever-changing technology standards and often produce characteristics that are relatively accurate at best. On the other hand, Field Programmable Gate Arrays are designed to simulate various forms of hardware, and can be analyzed for power usage directly. This project will explore the possibility of modeling the power characteristics of microprocessors by simulating their power usage on an FPGA by continuing research from the previous semester. Extent: 42 pages URI: http://arks.princeton.edu/ark:/88435/dsp01hx11xf359 Access Restrictions: Walk-in Access. This thesis can only be viewed on computer terminals at the Mudd Manuscript Library. Type of Material: Princeton University Senior Theses Language: en_US Appears in Collections: Electrical Engineering, 1932-2016

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