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Please use this identifier to cite or link to this item: http://arks.princeton.edu/ark:/88435/dsp01db78tf08d
Title: Sieve: Synthesis of Delay-Verifiable Two-Level Combinational Circuits
Authors: Lari, Ayla
Advisors: Jha, N.
Department: Electrical Engineering
Class Year: 1994
Extent: 33 Pages
Other Identifiers: 5620
URI: http://arks.princeton.edu/ark:/88435/dsp01db78tf08d
Location : This thesis can be viewed in person at the Mudd Manuscript Library. To order a copy complete the Senior Thesis Request Form. For more information contact mudd@princeton.edu.
Type of Material: Princeton University Senior Theses
Appears in Collections:Electrical Engineering, 1932-2016

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